The invention relates to memory devices. More particularly, the invention relates to memory array architectures and to dynamic cell plate sensing.
A DRAM memory cell includes a MOS access transistor and a storage capacitor. The access transistor is located between the memory cell capacitor and a digit line. The digit line is coupled to a plurality of memory cell transistors. Typically, either metal or polysilicon is used to form the digit line. The memory cell holds one bit of binary information, as stored electric charge in the cell capacitor. Given a bias voltage of Vcc/2 on the capacitor""s common node, a logical one is represented by +Vcc/2 volts across the capacitor and a logical zero is represented by xe2x88x92Vcc/2 volts across the capacitor.
The access transistor has a gate coupled to a word line. The word line is coupled to a plurality of memory cells, and is an extended segment of the same polysilicon used to form the access transistor""s gate. The word line is physically orthogonal to the digit line.
Digit lines are typically fabricated as pairs. The digit lines are initially equilibrated at Vcc/2 volts, and all word lines are initially at zero volts, which turns off the memory cell access transistors. To read a memory cell, its word line transitions to a voltage that is at least one transistor Vth above Vcc. This elevated word line voltage level is referred to as Vccp or Vpp. When the word line voltage exceeds one Vth above the digit line equilibrate voltage (Vcc/2) and the memory cell access transistor turns on, the memory cell capacitor begins to discharge onto a digit line. Reading or accessing a memory cell results in charge being shared between the memory cell capacitor and the digit line capacitance. This sharing of charge causes the digit line voltage to either increase for a stored logic one or decrease for a stored logic zero. Ideally, the access will only modify the active digit line, leaving its complement digit line unaltered. Thus, differential voltage develops between the two digit lines.
After the cell access is complete, a sensing operation is performed by a differential sense amplifier. The sense amplifier typically includes a cross-coupled PMOS transistor pair and a cross-coupled NMOS transistor pair. A signal voltage develops between the digit line pair when the memory cell access occurs. While one digit line contains charge from the cell access, the other digit line serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp fires first and the P-sense-amp second.
In another memory architecture, a common plate of the array of memory cell capacitors is used as a reference for the sense amplifier circuitry. In this type of architecture, the common plate is held at a predetermined voltage during operation.
The invention relates most particularly to memory architectures of a type having individual cell plate lines instead of the type where the cell plate line is the upper contact of the memory cell capacitor and all upper contacts are tied together on cell poly.
Attention is directed to the following patents, which describe dynamic cell plate sensing and which are incorporated herein by reference: U.S. Pat. No. 5,862,072 to Raad et al.; U.S. Pat. No. 5,862,089 to Raad et al.; and U.S. Pat. No. 5,821,895 to Manning. Attention is also directed to U.S. Pat. No. 5,841,691 to Fink, which relates to cell plate generators, and which is incorporated herein by reference.
Two problems exist in the individual plate line architecture. First, if both the bit line and the plate line were latched by a common sense amp, adjacent un-accessed storage cells can be corrupted. Specifically, a zero in an un-accessed storage cell could be coupled down to xe2x88x92DVC2. This would then turn on the access device of the un-accessed storage cell thereby leaking the zero up. Another problem which can occur in this type of architecture, is that the digit line and the plate line, upon firing of a word line, will move in opposite directions and thereby place, if allowed to, a full Vcc across the memory cell. This undesirably places a full Vcc across the nitride which serves as the cell dielectric. This can lead to breakdown and other problems which render the device inoperative.
The invention provides a method of operating a dynamic random access memory. One method includes turning on one equilibration transistor, while another equilibration transistor is off, so that a plate line equilibrates to a voltage defined by an equilibration voltage source during accessing of a memory cell.
One aspect of the invention provides a dynamic random access memory. The dynamic random access memory includes a plate line, a digit line, and a memory cell selectively coupled between the digit line and the plate line. Sense circuitry is selectively coupled to the memory cell to read the memory cell. The sense circuitry is capable of applying a first voltage from the plate line to the digit line. Equilibration circuitry selectively couples the plate line to an equilibration voltage less than the first voltage and selectively couples the digit line to the equilibration voltage. Control circuitry is configured to cause the equilibration circuitry to couple the plate line to the equilibration voltage while the memory cell is being accessed.
Another aspect of the invention provides a method of manufacturing a dynamic random access memory. The method includes providing control circuitry configured to turn on the first and second equilibration transistors to couple the digit line and plate line to the equilibration voltage source; turn off the first and second equilibration transistors, causing the digit line and plate line to float; turn on the access transistor; read the memory cell with the sense circuitry by determining the amount of charge on the capacitor; and turn on the second equilibration transistor, while the first equilibration transistor is off, so that the plate line equilibrates to the voltage defined by the equilibration voltage source.